1. Field of the Invention
This invention relates to a serial interface memory device that outputs data serially.
2. Description of the Related Art
In general, in the serial interface memory device, an address signal is serially inputted in synchronization with a rising edge of an external clock. The serial interface memory device is configured so that data stored in a memory cell array at an address defined by the address signal is read out with a sense amplifier when a last bit of the address signal is inputted in synchronization with the rising edge of the external clock, and the data is serially outputted from a first bit in synchronization with a falling edge of the external clock. A memory device of an eight-bit data width is configured to output eight-bit data serially, for example.
There is a limit to increasing a read-out rate, however, since the serial interface memory device is required by its specifications to read out the first bit data and start outputting the data within a ½ clock period after the last bit of the address signal is established.
Thus, there is conceived a method in which data at two candidate addresses are read ahead when the address signal of a bit that is one bit ahead of the last bit is inputted. Out of the data at the two candidate addresses which have been read ahead, data at an eventually determined address is outputted after the last bit of the address signal is established. In order to read ahead the data at the two candidate addresses, there are provided two sense amplifiers that correspond to the two addresses (Refer to Japanese Unexamined Patent Publication No. 2002-515628, for example.).
In the conventional serial interface memory device, however, there is a problem that its circuit becomes large and a size of a semiconductor die is increased, because the sense amplifiers to read ahead the data at the candidate addresses are additionally provided.